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This file is automatically generated by Xilinx. I haven’t used Zynq before, so maybe this suggestion is not appropriate. I’ve tried your device tree example as well as different examples found:. Reluctant to pursue it as we are not using Petalinux: Please upgrade to a Xilinx. There was a little communication confusion with Xilinx.

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Solved: Dual Marvell 88e PHY Ethernet problem – Xilinx – Community Forums

Add the phy handle to the gem sections: It will be fixed in the I’ve tried your device tree example as well as different examples found:.

I assume you use the same interface voltage for both PHY chips. Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it mravell related.

Again, this appears to be a software issue. Reluctant to pursue it as we are not using Petalinux:.

I will dig into the kernel code to see if there is a workaround. FYI, Tool and Software tags: The state machine for this is pretty simple and basically counts the bits as they go out and just inverts the value for one bit period during the desired address bit for example bit 1. However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth This patch is not yet available in the mainline and is expected to be available in the next release.


It will doubtless require changes to the linux driver stack to get it working.

net: phy: marvell: fix Marvell 88E used in SGMII mode – Patchwork

We are not amrvell to run our dual GEM config. With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the second PHY with address 1 valid address remains not configured and is fully not accessible.

Did you try running ping with u-boot? Have you tried with slightly rearranged device tree marvel, this? Could you explain how to linus Xilinx provided patch at each these different steps?

We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. Verified fix for this problem. Haven’t worked on this in a couple of years. When we get back to the issue I will post whatever resolution we come up with.

ChromeFirefoxInternet Explorer 11Safari. According to a Xilinx FAE: I haven’t used Zynq before, so maybe this suggestion is not appropriate. All forum topics Previous Topic Next Topic. I have verified that I can read the OUI bits from the PHY registers using u-boot ,inux read 0 2, mdio read 1 2 – other addresses do not respond.


net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]

We put our effort to fix this issue on hold, so I don’t have a solution for you. Anyone else had it work? Oddly, eth1 seems to receive packets even though the link is never detected.

I cant try it due to marfell situation, if you try it can you please give information about What other kernel settings did you have to enable to allow the Marvell 88e PHY to have the correct drivers from petalinux? Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.

I recommend the device tree in the answer with any necessary modifications for your implementation. I’ll update you when I have more information.